RISC-V Assembly Language Programming

Introduction

“RISC-V Assembly Language Programming: Unlock the Power of the RISC-V Instruction Set” is my fourth Assembly Language programming book published by Apress, a division of Springer Nature. This book is part of their Maker Innovations Series. My first three books were on the three types of ARM instruction sets, namely 32-bit, 64-bit and thumb (used in microcontrollers). The RISC-V instruction set architecture is more unified, so with this new book, I could cover both 32-bit and 64-bit RISC-V Assembly Language.

Update 2024/04/04: The source code is now in Apress’s github at: https://github.com/Apress/RISC-V-Assembly-Language-Programming

Update 2024/04/03: While waiting for Apress to upload the source code for the book, I placed it here: https://github.com/smist09/riscv-assembly-language/tree/main.

What is RISC-V?

Today’s CPU market is dominated by ARM and Intel. If you want to make your own CPU based on ARM then the royalties can be quite expensive and the terms restrictive on what you are allowed to do. Intel doesn’t like to license their CPU instruction set. There are a number of CPU also-rans such as MIPS that you might be able to license cheaper, but these are getting old and not being updated as much.

RISC-V was developed at Berkeley University. It is an instruction set architecture (ISA) that specifies the RISC-V Assembly Language instruction set and how the instructions are encoded to be executed. There are no royalties on using this architecture, so anyone can implement a RISC-V CPU and manufacture it. Designing and manufacturing a CPU can be expensive and there are a number of companies that have developed CPU designs that you can license and customize for your specific needs. One cool thing is that many people have implemented RISC-V CPUs in Verilog to run on various FPGA boards, something you don’t see in the ARM or Intel world.

Currently RISC-V is doing quite well in the microcontroller market, where CPUs often cost less than a dollar and licensing costs can sink a product. My RISC-V book includes how to program these microcontrollers such as the ESP32-C3 in 32-bit RISC-V Assembly Language.

RISC-V CPUs are starting to enter the desktop/laptop market with products like the StarFive VisionFive II which run 64-bit Debian Linux. My book covers programming these in 64-bit Assembly Language.

The RISC-V specification was released in 2010 and as such is the most modern RISC architecture available. It is an extensible architecture and many useful extensions have been released to support things like GPUs, AI coprocessors and other advanced functionality. When writing RISC-V Assembly Language, it feels much cleaner than either ARM or Intel. It is built on the legacies of all the previous RISC architectures including ARM, Mips, Sparc and Power and developed something quite remarkable.

The RISC-V architecture is still in the early stages and there are many opportunities to provide Assembly Language code to projects like the RISC-V Linux, GCC RISC-V target, bootloaders and firmware for all the new computing boards.

Where to Buy

As the book pushes its way out into the channel, it takes time to appear in all markets. As of today, it appears for sale on Springer Link, but is still pre-order at all the other retailers. Over the coming weeks they will start to change from pre-order to regular order as they receive their shipments. So apologies for anyone keen to buy, whose favorite retailer is still pre-order, but this should sort itself out over the next month. Here are a few links to some bigger retailers:

• Springer Link
• Amazon.com
• Amazon.ca
• Amazon.co.uk
• Chapters/Indigo
• Barnes & Noble

Summary

Writing this RISC-V Assembly Language Programming book was a lot of fun. I greatly enjoyed writing RISC-V Assembly Language programs and I hope you do as well. I’m sure that as time goes by, we’ll be seeing many more RISC-V CPUs filling all the available niches in the computing world. Before long there will be RISC-V mobile phones, laptops, desktops and even supercomputers.